Random Access Memory, commonly known as RAM, is a crucial component in modern digital systems. It allows for the temporary storage and retrieval of data in electronic devices. Designing RAM in VHDL (VHSIC Hardware Description Language) is a crucial skill for any digital design engineer, and in this article, we will discuss how to design RAM in VHDL using ModelSim, a popular simulation tool.
If you are beginner in VLSI and VHDL, you should go with this article: Getting Started with VLSI and VHDL using ModelSim – A Beginners Guide
Before we dive into designing RAM, let us first understand what it is and how it works. RAM is a type of memory that allows for data to be stored and retrieved in any order, hence the term 'random access.' RAM is made up of a series of storage locations, each of which can store a single bit of data. These storage locations are organized into words, with each word containing a fixed number of bits. The size of the RAM is determined by the number of words it contains, and the size of each word is determined by the number of bits in each storage location.
In VHDL, RAM can be designed using two methods: behavioral and structural. The behavioral method involves describing the functionality of the RAM in terms of its inputs and outputs, while the structural method involves describing the physical layout of the RAM using subcomponents.
For this article, we will focus on the structural method of designing RAM in VHDL using ModelSim. We will design a 4-bit RAM with 4 words, each word consisting of four bits. The RAM will have two input ports: the address bus and the data bus. The address bus will consist of two bits, while the data bus will consist of four bits. The RAM will have two output ports: the data out port and the read enable port.
The first step in designing the RAM is to create a new VHDL file in ModelSim. We will name this file 'RAM.vhd'. Once the file is created, we will begin by defining the inputs and outputs of the RAM using the 'port' keyword.
entity RAM is
port (address: in std_logic_vector(1 downto 0);
data_in: in std_logic_vector(3 downto 0);
data_out: out std_logic_vector(3 downto 0);
read_en: in std_logic);
end entity RAM;
Next, we will define the internal signals of the RAM using the 'signal' keyword. We will define a signal for each storage location in the RAM, and each signal will be four bits wide to store one word of data.
architecture Behavioral of RAM is
signal word0, word1, word2, word3: std_logic_vector(3 downto 0);
begin
-- RAM logic goes here
end architecture Behavioral;
After defining the signals, we will move on to the logic of the RAM. The logic of the RAM will consist of two processes: the write process and the read process.
The write process will be triggered when the read enable port is low, indicating that the RAM is in write mode. The write process will use the address bus to select the appropriate storage location, and the data bus to write the data into that location.
write_process: process (address, data_in, read_en)
begin
if read_en = '0' then -- RAM is in write mode
case address is
when "00" => word0 <= data_in;
when "01" => word1 <= data_in;
when "10" => word2 <= data_in;
when "11" => word3 <= data_in;
end case;
end if;
end process write_process;
The read process will use the address bus to select the appropriate storage location, and the data out port to output the data stored in that location.
read_process: process (address, read_en)
begin
if read_en = '1' then -- RAM is in read mode
case address is
when "00" => data_out <= word0;
when "01" => data_out <= word1;
when "10" => data_out <= word2;
when "11" => data_out <= word3;
end case;
end if;
end process read_process;
Finally, we will end the architecture block by specifying the behavior of the RAM. In this case, the RAM will simply consist of the write and read processes.
architecture Behavioral of RAM is
signal word0, word1, word2, word3: std_logic_vector(3 downto 0);
begin
write_process: process (address, data_in, read_en)
begin
if read_en = '0' then -- RAM is in write mode
case address is
when "00" => word0 <= data_in;
when "01" => word1 <= data_in;
when "10" => word2 <= data_in;
when "11" => word3 <= data_in;
end case;
end if;
end process write_process;
read_process: process (address, read_en)
begin
if read_en = '1' then -- RAM is in read mode
case address is
when "00" => data_out <= word0;
when "01" => data_out <= word1;
when "10" => data_out <= word2;
when "11" => data_out <= word3;
end case;
end if;
end process read_process;
end architecture Behavioral;
Once the VHDL file is complete, we can simulate the RAM design using ModelSim. We can create a testbench file to apply inputs to the RAM and observe the outputs. We can then use the ModelSim waveform viewer to visualize the behavior of the RAM.
In conclusion, designing RAM in VHDL using ModelSim is an essential skill for digital design engineers. The structural method of designing RAM allows for the physical layout of the RAM to be described using subcomponents, making it easier to understand and modify. By following the steps outlined in this article, we can design and simulate a 4-bit RAM with 4 words, each word consisting of four bits, using VHDL and ModelSim.
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